1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof and more specifically relates to a double gate transistor and method of fabricating the double gate transistor.
2. Description of the Related Art
The metal oxide semiconductor field effect transistor (MOSFET) technology is a currently-used primary electronic device technology. Generally, a dimension of a device is reduced to enhance the speed of the device, thereby realizing improvements in performance between devices of each subsequent generation. This is typically called “shrinkage in scale” of a device.
Ultra large scale integrated (ULSI) circuits generally comprise a great number of transistors which cooperate to perform various functions for an electronic device, wherein a complementary metal oxide semiconductor field effect transistor (CMOSFET) that includes a gate disposed between source and drain regions is most frequently used. The gate is provided on a gate oxide material. Generally, a material used to form the gate can be a metal or a poly-material such as poly-silicon, poly-germanium or poly-silicon germanium (SixGe1-x), which controls the charge carrier in a channel region between the drain and source regions so as to turn a transistor on or off. The transistor can be an N-channel MOSFET or a P-channel MOSFET.
In a conventional MOSFET, source and drain regions are formed by doping a substrate; a gate is used for controlling current in a channel region. As a MOSFET is shrunk in scale to a channel length below 100 nm, a lot of problems occur for the conventional MOSFET. One major problem is that the interaction between the source and drain regions of the MOSFET decreases the ability of a gate to control the on or off state of a device, which is a phenomenon called “short channel effect (SCE).” It is difficult to overcome problems related to the short channel effect such as leakage current between source and drain regions as well as reduction of mobility.
Multi-gate MOSFETs have gates at multiple sides of a channel and thus can control gates from multiple sides, thereby reducing the SCE and increasing driving current. FIG. 1 schematically shows four structures for a double gate, a trigate, an Ω gate and a quadgate MOSFET.
As shown in FIGS. 1A-1D, the prior art multi gates 11G, 12G, 13G, 14G, respectively, are a double gate, a tri-gate, an Ω gate and a quadri-gate MOSFET 11, 12, 13, 14 are connected together and controlled by the same electrode, which is a disadvantage for separately controlling the multiple gates.
In addition, during the operation of the MOSFET device, in order to enhance carrier mobility of the device, a stress is typically applied on the channel region. However, in prior art multi-gate MOSFETs provided, it is difficult to effectively apply a desired stress on the channel region.